An Optimization of Hybrid Soft Bit Flipping algorithm: An Experimental Approach

The advanced digital communication system encodes the digital data transmissions over communication channel, and then decodes the receiving end messages. The effective data transfer and error free data at the receiving end require decoding algorithms, which in turn process LDPC codes and efficient detection. Various algorithms used for decoding the Euclidean Geometric (EG)-LDPC codes, such as Soft Bit Flipping (SBF) algorithm, Majority Logic Decoder/Detector (MLDD) algorithm, Belief Propagation Decoding (BPD), Sequential Peeling Decoding (SPD) and Parallel Peeling Decoding (PPD) algorithms. In order to address the trade-offs among decoding latency, hardware complexity, and power consumption, a novel hybrid decoding scheme is proposed. Thus, a Self-Reliability based Weighted Soft-Bit-Flipping Algorithm (SRWSBF) is proposed in this research as a high performance algorithm for decoding of EG-LDPC codes with low complexity. The proposed simulation model is formulated by employing the Xilinx ISE and SPARTAN 3e for investigating the latency, hardware utilization and power consumption. A significant change is found that an average of 16.65% latency is minimized compared to the existing decoding algorithms. The hardware minimization is also achieved at an average of 10.74% compared to existing algorithms. The noticeable achievement in this research is minimization of power consumption at an average of 41.68 % over the existing decoding algorithms. Thus, the proposed algorithm makes significant contribution for improving the message transfer in terms of decoding latency, hardware complexity and power consumption.